How to separate makefile assembly outputs for different configurations?

Question

Given that I have a project with a simple Makefile, for example:

all: foobar
foobar: foo.o bar.o

which I can create for different architectures:

$ CC=clang make                    # or
$ CC=x86_64-w64-mingw32-gcc  make  # or
$ CC=arm-linux-gnueabihf-gcc make

This works, but I want to be able to support outputs for multiple configurations at the same time, for example, on the build server.

What would be a good, clean way to do this? I reviewed the following:

• Use autotools or another build tool, but I want to see what is possible without
• Create build directories using Make files in them that install VPATH and include the root Makefile
• Write a script that moves the output after building each architecture
• Makefile . , -Makefile, .
• Makefile, . , , Makefile. .

Answer 1

- :

# User configuration
BINARY  := hello
SOURCES := main.c

# Create the output paths
out     ?= out
outdir  := $(out)/$(CC)
outbin  := $(outdir)/$(BINARY)
objects := $(outdir)/$(SOURCES:.c=.o)

# Default target
all: $(outbin)

# Binary target
$(outbin): $(objects)
    $(CC) -o $@ $^

# Objects target
$(objects): $(outdir)/%.o: %.c
    mkdir -p $(@D)
    $(CC) -o $@ -c $<

# The cleanning targets
clean:
    $(RM) -r $(outdir)

mrproper:
    $(RM) -r $(out)

# Declare phony targets
.PHONY: all clean mrproper

, target , .

---

Makefile:

$ make
mkdir -p out/cc
cc -o out/cc/main.o -c main.c
cc -o out/cc/hello out/cc/main.o

$ make
make: Nothing to be done for 'all'.

$ tree
.
├── main.c
├── Makefile
└── out
    └── cc
        ├── hello
        └── main.o

2 directories, 4 files

$ CC=gcc make
mkdir -p out/gcc
gcc -o out/gcc/main.o -c main.c
gcc -o out/gcc/hello out/gcc/main.o

$ tree
.
├── main.c
├── Makefile
└── out
    ├── cc
    │   ├── hello
    │   └── main.o
    └── gcc
        ├── hello
        └── main.o

3 directories, 6 files