Lexing VHDL (tick)

Question

In VHDL, this character can be used to encapsulate a character token, ie '.'or it can be used as an attribute separator (similar to CPP :: token) ie string'("hello").

The problem occurs when parsing the attribute name containing the character ie string'('a','b','c'). In this case, the naive lexer will incorrectly mark the first '('as a character, and the entire next actual character will be corrupted.

In the list of comp.lang.vhdl google group there is a stream in 2007 that asks a similar question called "Lexing" char " , which has a response by diogratia

        case '\'':                          /* IR1045 check */

            if (    last_token == DELIM_RIGHT_PAREN ||
                    last_token == DELIM_RIGHT_BRACKET ||
                    last_token == KEYWD_ALL ||
                    last_token == IDENTIFIER_TOKEN ||
                    last_token == STR_LIT_TOKEN ||
                    last_token == CHAR_LIT_TOKEN || ! (buff_ptr<BUFSIZ-2) )
                token_flag = DELIM_APOSTROPHE;
            else if (is_graphic_char(NEXT_CHAR) &&
                    line_buff[buff_ptr+2] == '\'') { CHARACTER_LITERAL:
                buff_ptr+= 3;               /* lead,trailing \' and char */
                last_token = CHAR_LIT_TOKEN;
                token_strlen = 3;
                return (last_token);
            }
            else token_flag = DELIM_APOSTROPHE;
            break;

See error report IR1045: http://www.eda-twiki.org/isac/IRs-VHDL-93/IR1045.txt

, -:

  foo <= std_logic_vector'('a','b','c');

.

, , flex , .

, lexing?

IntelliJ GrammarKit, .

Answer 1

IR1045 , , / , , , :

library ieee;
use ieee.std_logic_1164.all;

entity foo is
    port (
        a:      in      std_logic;
        b:      out     std_logic_vector (3 downto 0)
    );
end entity;

architecture behave of foo is
    begin
    b <= std_logic_vector'('0','1','1','0')     when a = '1' else
         (others =>'0')                         when a = '0' else
         (others => 'X');
end architecture behave;

?

VHDL.

Nick Gasson nvc flex, 1045.

nvc/src/lexer.l, GPLv3.

last_token:

#define TOKEN(t) return (last_token = (t))

#define TOKEN_LRM(t, lrm)                                       \
   if (standard() < lrm) {                                      \
      warn_at(&yylloc, "%s is a reserved word in VHDL-%s",      \
              yytext, standard_text(lrm));                      \
      return parse_id(yytext);                                  \
   }                                                            \
   else                                                         \
      return (last_token = (t));

​​ :

static int resolve_ir1045(void);

static int last_token = -1;

:

%%

static int resolve_ir1045(void)
{
   // See here for discussion:
   //   http://www.eda-stds.org/isac/IRs-VHDL-93/IR1045.txt
   // The set of tokens that may precede a character literal is
   // disjoint from that which may precede a single tick token.

   switch (last_token) {
   case tRSQUARE:
   case tRPAREN:
   case tALL:
   case tID:
      // Cannot be a character literal
      return 0;
   default:
      return 1;
   }
}

IR1045 comp.lang.vhdl

http://www.eda-twiki.org/isac/IRs-VHDL-93/IR1045.txt

resol_ir1045 lexer.l.

static int resolve_ir1045(void);

{CHAR}            { if (resolve_ir1045()) {
                       yylval.s = strdup(yytext);
                       TOKEN(tID);

, nvc .

. IR-1045 , . , , Ada flex, .

Ada 27 3 2006 PDF 30 31 ( 27 . 159 160), , .

, , :

entity ir1045 is
end entity;

architecture foo of ir1045 is
begin
THIS_PROCESS:
    process
        type twovalue is ('0', '1');  
        subtype string4 is string(1 to 4);
        attribute a: string4;
        attribute a of '1' : literal is "TRUE";
    begin
        assert THIS_PROCESS.'1''a /= "TRUE"
            report "'1''a /= ""TRUE"" is FALSE";
        report "This_PROCESS.'1''a'RIGHT = " &
            integer'image(This_PROCESS.'1''a'RIGHT);
        wait;
    end process;
end architecture;

, , , , , :

ghdl -a ir1045.vhdl
ghdl -e ir1045
ghdl -r ir1045
ir1045.vhdl:13:9:@0ms:(assertion error): '1''a /= "TRUE" is FALSE
ir1045.vhdl:15:9:@0ms:(report note): This_PROCESS.'1''a'RIGHT = 4

, , , "" ( entity_class, . IEEE Std 1076-2008 7.2) , .

VHDL. , nvc . 7.2.

, twovalue. , , (5.2.2.1).