Why use xzr instead of literal 0 on ARMv8?

Question

I read the ARM SVE whitepaper and came across something that seemed odd to me (in an example other than SVE):

mov x8, xzr

I did not know what this register was xzr, so I looked at it and found some content from ARM , indicating that it was synonymous with zero in many contexts.

So it looks like it is x8initialized to zero, which makes sense because it runs just before the loop, where it is x8used as a loop counter.

What I don’t understand, why xzrnot literal was used instead 0? For instance:

mov x8, 0

To summarize, my question is: why use case xzrinstead of literal 0here?

Answer 1

I think the mov x8, xzrvs comparison mov x8, #0is a bit of a red herring.

As @old_timer’s answer shows, there is no coding gain, and most likely (although admittedly I haven’t checked) the system performance is little or not achieved.

Which xzrgives us, however - in addition to dummy registration according to @InfinitelyManic, the answer is access to the null operand without having to load and occupy the real register. This has the double benefit of one smaller instruction, and another register is available for storing "real" data.

, , ' ARM, OP.

, mov x8, xzr vs mov x8, #0, . x8 , xzr #0 ( #0 ). x8 , , - - xzr x8 x8 .

Answer 2

mov x8,xzr
mov x8,#0
mov x8,0

0000000000000000 <.text>:
   0:   aa1f03e8    mov x8, xzr
   4:   d2800008    mov x8, #0x0                    // #0
   8:   d2800008    mov x8, #0x0                    // #0

, , . ( , x86, , xor rax, rax , mov rax, 0), , ( , , ).

, , , , .

Answer 3

- , .

.

mov x8, 0 orr x8, xzr, 0

mov x8, xzr orr x8, xzr, xzr

, ASM .

, xzr . , xzr , orr mov. mov , .

Answer 4

" " OP.

XZR ; , "ldr xzr, [sp], 16". . GDB

0x7fffffef40:   0x00000000      0x00000000      0x00400498      0x00000000
0x7fffffef50:   0x00000000      0x00000000      0x00000000      0x00000000
              ldr x0,=0xdead
(gdb)
              ldr x1,=0xc0de
(gdb)
              stp x0, x1, [sp, #-16]!
(gdb) x/8x $sp
0x7fffffef30:   0x0000dead      0x00000000      0x0000c0de      0x00000000
0x7fffffef40:   0x00000000      0x00000000      0x00400498      0x00000000

              ldr xzr, [sp], #16
(gdb) x/8x $sp
0x7fffffef40:   0x00000000      0x00000000      0x00400498      0x00000000
0x7fffffef50:   0x00000000      0x00000000      0x00000000      0x00000000

, ARMv8 SP mod 16 = 0. , XZR "push" "popped".

stp x1, xzr, [sp, #-16]!

ldp x10, xzr, [sp], #16

Answer 5

TL; DR

64- , 0 zxr. .

---

, MOVL, . :

- MOVL

:

A 32-bit or 64-bit immediate value.

Any address.

MOVL ... MOV, MOVK.

, - . , . zxr - , , , , .

Microchip- . , - :

MOVLW   10       (Move 10 to the working register) 
MOVWF   0x1234   (Move the working register to address 0x1234)

:

CLRF    0x1234   (Set 0x1234 to zero)