Does the security barrier provide cache integrity?

Question

Say I have two threads that control a global variable x. Each thread (or each core, I suppose) will have a cached copy x.

Now say that you Thread Aare following these instructions:

set x to 5
some other instruction

Now, when executed set x to 5, the cached value xwill be set to 5, this will cause the cache coherence protocol to act and update the caches of other kernels with a new value x.

Now my question is: when it xis actually installed in 5the cache Thread A, are the caches of other kernels updated before they are executed some other instruction? Or should a memory barrier be used for this ?:

set x to 5
memory barrier
some other instruction

Note. . Suppose that the instructions were executed in order, also suppose that when executed it is set x to 5 5immediately placed in Thread A` cache (therefore, the instruction was not queued or something that will be executed later).

Answer 1

The memory gateways are present in the x86 architecture, but this in general - not only ensures that all previous downloads or repositories ¹ are completed before any subsequent download or storage is performed - they also ensure that stores become globally visible .

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Memory ordering -- enforces --> Global visibility -- needs -> Cache coherency
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Answer 2

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Answer 3

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What is a memory barrier or a barrier + op, this ensures that the operation will be visible to other agents in a relative order, which obeys all the restrictions of the barrier. This, of course, usually does not imply pushing the result to other processors as a matching operation, which you doubt.