AVR timer overflow interruption not working

Question

Hi, nice people. My problem is the interrupt service routine (ISR), which apparently never runs! Here is some information about my setup: I sparkle avr attiny85. I have the bare bones of a project created so far with a simple main.c and two modules: timer and hardwareInit. In the timer module, I have a timer0_init function that I use to set timer0 for CTC mode to overflow for just 1 ms. Here is the function:

void timer0_init( void )
{
    cli();
    TCCR0B |= 3;    //clock select is divided by 64.
    TCCR0A |= 2;    //sets mode to CTC
    OCR0A = 0x7C;   //sets TOP to 124 so the timer will overflow every 1 ms.    
    TIMSK |= 2;     //Enable overflow interrupt
    sei();          //enable global interrupts
}

with a timer setting, I added an ISR to increase ticks every time the counter overflows, so I can track how much time has passed, etc.

ISR(TIMER0_OVF_vect)
{
    cli();
    //ticks ++;
    PORTB |= ( 1 << PORTB0 );   
    sei();
}

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, main.c:

/*================================= main.c =================================*/

#define F_CPU   8000000UL

#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>

#include "timer.h"
#include "hardwareInit.h"


int main(){

    //Initialize hardware HERE  
    DDRB |= ( 1 << PORTB0 );    //set this pin as an output for an LED

    SetClockPrescale(1);    //internal clock divided by 1 = 8 MHz, from hardwareInit

    timer0_init();          //set up timer0 for 1 ms overflow


    while(1)
    {
        /* if( getTicks() > 0 )
        {
            PORTB |= ( 1 << PORTB0 );
            _delay_ms(1000);
            PORTB &= ~( 1 << PORTB0 );
            _delay_ms(1000);
        } */

    }
    return 0;
}

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Answer 1

ISR, @andars . CTC "Clear Timer on Compare" , .

, . 1 TIMSK 0. . datasheet.

OCR0A , 4 - OCIE0A: / 0 .

ISR, ISR(TIMER1_COMPA_vect) ISR(TIMER1_COMPB_vect) , TIMSK. , , OCR0A OCR0B.

---

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, :

void timer0_init( void )
{
    cli();          
    TCCR0B |= (1<<CS01) | (1<<CS00);   //clock select is divided by 64.
    TCCR0A |= (1<<WGM01);              //sets mode to CTC
    OCR0A = 0x7C;                      //sets TOP to 124 so the timer will overflow every 1 ms.    
    TIMSK |= (1<<OCIE0A);              //Output Compare Match A Interrupt Enable
    sei();                             //enable global interrupts
}

ISR:

ISR(TIMER0_COMPA_vect)
{
    cli();
    //ticks ++;
    PORTB |= ( 1 << PORTB0 );   
    sei();
}