Is there a simple example of creating a verilogue from the Chisel3 module?

Question

I am looking for an easy way to convert a simple Chisel3 module to Verilog.

I take the Gcd source code indicated on the official bit web page.

  import chisel3._

  class GCD extends Module {
    val io = IO(new Bundle {
      val a  = Input(UInt(32.W))
      val b  = Input(UInt(32.W))
      val e  = Input(Bool())
      val z  = Output(UInt(32.W))
      val v  = Output(Bool())
    })
    val x = Reg(UInt(32.W))
    val y = Reg(UInt(32.W))
    when (x > y) {
      x := x -% y
    }.otherwise {
      y := y -% x
    }
    when (io.e) {
      x := io.a
      y := io.b
    }
    io.z := x
    io.v := y === 0.U
  }

I can not find how to write build.sbt and an instance of the class to convert it to Verilog.

Answer 1

Thank you for your interest in the chisel! We generally recommend that people use our chisel-based repository as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template.

If you want to make as many skeletons as possible. Create this build.sbt and put it in the root directory of your project.

scalaVersion := "2.12.8"

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.1.+"

GCD GCD.scala :

object GCDDriver extends App {
  chisel3.Driver.execute(args, () => new GCD)
}

Verilog, : sbt "runMain GCDDriver". - >

, , sbt "runMain GCDDriver --help" , --target-dir