VHDL - Why does using the length attribute directly in a function raise a warning?

Question

I have a VHDL function that returns a view of the std_logic_vector entry, and I want the length of this std_logic_vector. I can use the length attribute directly in the function. Why does this cause a warning in ModelSim? Do I suggest subtle issues? The incorrect display of the warning text did not show anything useful.

my_function_returns_slv(my_record)'length;

** Warning: ../ src / my.vhd (line #): (vcom-1515) Prefix of the predefined attribute "length" - this function call "my_function_returns_slv"

I wrote a function to assemble the output by concatenating the representations of the std_logic_vector entries. The length of the record is fixed at compile time, but I do not want to hardcode the length. I need length to create signals for using function output. Therefore, I can’t just call the “length at the output of the function (for example: the“ call length ”to the signal containing the output of the function), because it is impossible to declare an unlimited signal to output the output. I could write a similar function to calculate the length of std_logic_vector, but this will add some significant code, especially for the number of records that I have. Should I accept the ModelSim warning and continue? Should I work with additional code from writing functions to collect the bit width of my records? Is there a better solution?

/ :

http://www.eda-twiki.org/twiki/pub/P1076/RecordReflectionToSlv/standard_functions.vhd

!

Answer 1

'length , , .

, ModelSim, , , , , . , .

, ModelSim, :

function len(slv : std_logic_vector) return natural is
begin
  return slv'length;
end function;

ModelSim:

signal MY_LEN : natural := len(slv_not(CONST));

, , .

Answer 2

" . " " (:" " , ), ."

:

constant MY_CONST : std_logic_vector := my_function_returns_slv(my_record) ;
signal MySig : std_logic_vector(MY_CONST'range) := MY_CONST ; 

LCS VHDL-2017, .