Preferred syntax for verilog module declaration

Question

I am relatively new to FPGA and I am looking for some recommendations for current best practice regarding module declarations in Verilog.

I saw two ways to declare a module in verilog. The first reminds me of Traditional C , for example, examples on wikipedia :

module toplevel(clock,reset);
    input clock;
    input reset;

    /* snip */
endmodule

While the alternative syntax has an I / O specifier as part of the argument list, not too different from VHDL, as in this example :

module fadder(
    input a,         //data in a
    input b,         //data in b
    input cin,       //carry in
    output sum_out,  //sum output
    output c_out     //carry output
);

/* snip */
endmodule

Verilog, ? "", , -, ( , , ), . !

Answer 1

, . LRM 1364-2001 Verlog LRM, 1800- SystemVerilog LRM, , . , , , , .

( ANSI-) , . ; , , - , , .

Answer 2

. Verilog 2001. "ANSI-style".

Verilog, , ANSI- . ( , , .)

System-Verilog, , ANSI-.

Answer 3

, , . , , , . . , localparam , .
, () Verilog, local_param # (..

module example 
#(parameter       
   L2DEPTH   =  8,
   OFFSET    =  2
)
(siga,sigb,sigc,sig_out);
localparam DEPTH = 1<<L2DEPTH;
localparan TOP   = DEPTH+OFFSET;
localparam BOT   = DEPTH-OFFSET;
localparam DBLDEPTH   = 2<<L2DEPTH;;
input  [  L2DEPT-1:0] siga;
input  [     TOP-1:0] sigb;
input  [     BOT-1:0] sigc;
output [DBLDEPTH-1:0] sig_out;