What is the $ (MAKE) variable in a makefile?

Question

I am currently learning how to write make files. I have the following makefile (which is automatically generated for a C project that should run on an ARM chip), and I'm trying to figure it out:

    RM := rm -rf

    # All of the sources participating in the build are defined here
    -include sources.mk
    -include FreeRTOS/Supp_Components/subdir.mk
    -include FreeRTOS/MemMang/subdir.mk
    -...
    -include subdir.mk
    -include objects.mk

    ifneq ($(MAKECMDGOALS),clean)
    ifneq ($(strip $(S_UPPER_DEPS)),)
    -include $(S_UPPER_DEPS)
    endif
    ifneq ($(strip $(C_DEPS)),)
    -include $(C_DEPS)
    endif
    endif

    -include ../makefile.defs

    # Add inputs and outputs from these tool invocations to the build variables 

    # All Target
    all: FreeRTOS_T02.elf

    # Tool invocations
    FreeRTOS_T02.elf: $(OBJS) $(USER_OBJS)
        @echo 'Building target: $@'
        @echo 'Invoking: MCU GCC Linker'
        arm-none-eabi-gcc -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 -specs=nosys.specs -specs=nano.specs -T LinkerScript.ld -Wl,-Map=output.map -Wl,--gc-sections -lm -o "FreeRTOS_T02.elf" @"objects.list" $(USER_OBJS) $(LIBS)
        @echo 'Finished building target: $@'
        @echo ' '
        $(MAKE) --no-print-directory post-build

    # Other Targets
    clean:
        -$(RM) *
        -@echo ' '

    post-build:
        -@echo 'Generating binary and Printing size information:'
        arm-none-eabi-objcopy -O binary "FreeRTOS_T02.elf" "FreeRTOS_T02.bin"
        arm-none-eabi-size "FreeRTOS_T02.elf"
        -@echo ' '

    .PHONY: all clean dependents
    .SECONDARY: post-build

    -include ../makefile.targets

I am trying to wrap my head around a line $(MAKE) --no-print-directory post-buildin a rule to create a file .elf.

I cannot find a definition for the variable $(MAKE), so I assume that it is something inline. What does this line really do?

Answer 1

make, -t, -n -q. : , make .

Answer 2

docs:

- , make

, - , make , - -t (--touch), -n (--just-print), -q (--question). , ($MAKE).

Answer 3

, , . $ MAKE - , "make".

And in your script, $ MAKE is used as part of the commands (recipe) of the makefile. This means that whenever a dependency change occurs, make executes the command "make --no-print-directory post-build" in the directory in which you are located .

For example, if I have a case where everything is test.c: test.c cd / root / $ (MAKE) It says that if there is a change in test.c, run the "make all" command in the / root directory.