CPSID i assembly instructions not supported by Cortex M0

Question

I am developing code for Cortex M0 using FreeRTOS and eclipse with the AC6 plugin. At the end of my tasks, I use assert to determine if the watermark of my task exceeds the specified size of the task. The macro I use for my statement is as follows:

#define HMI_DBG_ASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); \
                  HAL_GPIO_WritePin(ASSERT_LED_GPIO_Port, ASSERT_LED_Pin, GPIO_PIN_SET); \
                  for( ;; );}

My tasks are as follows:

for(;;)
{
    //some
    //code
    uxHighWaterMark = uxTaskGetStackHighWaterMark( NULL );
    HMI_DBG_ASSERT(uxHighWaterMark >= WDG_STACK_SIZE_WATERMARK_WORD);
}

This compiles and works great! My problem is that I am working on shared code with another developer, and he used a macro that is almost identical to mine:

#define CMN_DBG_ASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); \
                  HAL_GPIO_WritePin(ASSERT_LED_GPIO_Port, ASSERT_LED_Pin, GPIO_PIN_SET); \
                  for( ;; );}

When I call this macro, my compiler returns the following error:

selected processor does not support `cpsid i' in Thumb mode

"taskDISABLE_INTERUPTS ();" the macro is defined by FreeRTOS and invokes the following assembly instruction:

__asm volatile( " cpsid i " )

, , . , HMI_DBG_ASSERT .c , CMN_DBG_ASSERT, . , , eclipse .

Cortex-M wiki , "CPSIE CPSID , ARM Cortex-M. CPS Cortex-M".

ARM CPSIE CPSID Cortex-M0:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/BABHBAAB.html

, , , . , IAR Cortex-M, , ... .

- , ?

Answer 1

. - , , -mcpu . reset :

→ → reset