In systemverilog #, the delay does not work when the RHS signal changes faster than the delay

Question

The following code on the system device does not work:

module test_dly;
  reg clk = 0;
  wire w_clk_d;

  always #1ns  clk <= ~clk;
  assign #1400ps w_clk_d = clk;
endmodule

I expected w_clk_d to postpone the clk version, but that is not the case. It seems that # does not work if a new event arrives before the delay expires. I wrote code to handle this, but is there a way to make # work as expected? Thank,

Answer 1

assign #1400ps w_clk_d = clk; . clk 1400ps, ( ) w_clk_d. , . .

; .

wire   #700ps clk_d = clk;
assign #700ps w_clk_d = clk_d;

, clk , w_clk_d 1400ps last

logic w_clk_d;
always @* w_clk_d <= #1400ps clk;

,

logic w_clk_d;
always @(clk) fork
  begin
    automatic logic sample_clk; // visible only locally with in the fork thread
    sample_clk = clk; // local copy of clk
    #1400ps;
    w_clk_d = sample_clk;
  end
join_none // non-blocking, allows detection of next @(clk)

Answer 2

, assign . RHS , , , LHS .

- , : RHS LHS. (NBA).

module test_dly;
  reg clk = 0;
  wire w_clk_d;

  always #1ns  clk = ~clk;
  always @clk  w_clk_d <= #1400ps clk;
endmodule