Common in verilog from vhdl programmer

Question

What is equivalent to generic in verilog? for instance

entity my_entity
generic(a : integer);
port(x : in std_logic; y out std_logic);
end entity my_entity;

What is the equivalent for general? Also, what is the equivalent for if generating and generating?

Answer 1

Generics are called parameters in Verilog. They are declared inside the module as strings of the type:

parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;

Concretization can individually specify the values ​​of the parameters:

my_ram_impl #( 
  .DATA_WIDTH(16), 
  .ADDR_WIDTH(8)
)
ram_instance(
  .clk(clk),
  .addr(addr),
  .data(data),
  .cs(cs),
  .we(we)
); 

Use these directives similar to C for conditional synthesis:

`ifdef  SYM
   ...
`else
   ...
`endif

or, more flexibly generatecreates:

generate
  if(cond)
    ...
  else
    ...
endgenerate

Answer 2

core_top . NCORE - , .

  wire clk;
  wire [31:0] data_from_core[0:NCORES-1];

  genvar core;
  generate
    for (core=0; core < NCORES; core=core+1) begin : core_gen
         core_top
            #(.CORE_ID  (core),
              .NCORES   (NCORES))
           u_fpgaminer_top
             (.clk_in          (clk),
              .data_out        (data_from_core[core]));
      end
  endgenerate