Is it faster to increment a pointer than doing "mov [pointer + 1], eax"?

Say we want to save a string in EDI. It would be faster to save it that way.

mov byte [edi],0
mov byte [edi+1],1
mov byte [edi+2],2
mov byte [edi+3],3
...

or so?

mov byte [edi],0
inc edi
mov byte [edi],1
inc edi
mov byte [edi],2
inc edi
mov byte [edi],3
inc edi
...

Some may suggest the following in little-endian:

mov dword [edi],0x3210

Or the following in big-endian:

mov dword [edi],0x0123

But this is not a question of my question. My question is, is it faster to increment the pointer and then do mov, requiring more instructions, or faster to indicate in each mov command the amount added to the offset address pointed to by the EDI? If the latter is true, then after how many mov commands with the same number, to add to the offset address, will it cost to simply add this amount to the index? In other words, this

mov byte [edi+5],0xFF
mov byte [edi+5],0xFF
mov byte [edi+5],0xFF
mov byte [edi+5],0xFF

faster than that?

add edi,5
mov byte [edi],0xFF
mov byte [edi],0xFF
mov byte [edi],0xFF
mov byte [edi],0xFF
+4
1

http://agner.org/optimize/ wiki, , asm.


:

mov byte [edi],0
mov byte [edi+1],1
mov byte [edi+2],2
mov byte [edi+3],3
...

. AFAIK, . Intel SnB-, .

, gcc clang, ( ) .


BTW, 4- 0x03020100 4 , . 128- , 128b , 8b. AVX 256b - , 128- Intel SnB/IvB, Intel Haswell 256- . mov- 8, 16 32- . mov r64, imm64 64- , 128 256 mov- .


32- , inc reg, inc edi/mov byte [edi],1 , uops Intel AMD. , - , . , uops , , , , inc . , , , . , / .

64- inc rdx 3 : 1 REX 64- ( 32- ), 1 int r/m32 1 mod/rm byte rdx .

, 64- . inc uop- ( Intel SnB-), uops .


:

mov byte [edi+5],0xFF
mov byte [edi+5],0xFF
mov byte [edi+5],0xFF
mov byte [edi+5],0xFF

.

add edi,5            ; 3 bytes to encode.  (2 if it was eax)
mov byte [edi],0xFF  ; saving one byte in each instruction
mov byte [edi],0xFF
mov byte [edi],0xFF
mov byte [edi],0xFF

(), , . - , , uop. uop , . ( uop) , , 4. , .

+9

Source: https://habr.com/ru/post/1624207/


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