The next post is quite long, but since I had problems with the fact that the SP605 board interacted correctly with DDR3 for more than a month, we hope that it will be useful for others in the same situation I am in. quite definitely, this is a simple configuration or a conceptual error, but I would be more than happy if it were resolved in the near future.
=== SCENARIO ===
I created a USB-UART interface for FPGA communication and DDR3 control. Using the IP generator in ISE, I generated a MIG wrapper, and then I developed a memory interface controller. However, I referenced the ug388 and ug416 manuals, but I could not run DDR3 as expected.
=== STATEMENT OF THE PROBLEM ===
Playing with packet lengths for write and read commands, I can get data from DDR3, but the addressing scheme does not seem correct, because the data is duplicated at addresses 0 and 1, 2 and 3, 4 and 5, and so on. In addition, whenever I write to address 0, for example, nothing changes. Then, when I write to address 1, both addresses 0 and 1 are updated with the data value passed by me. I seem to be losing half of my memory due to this related effect.
=== DDR3 IP CONFIGURATION ===
The configuration for DDR3 using the IP generator - taking into account the scenario of the SP605 board - is given below. In general, I activated DDR3 Bank 3 and configured Port0 as 32-bit bidirectional.
Memory selection:
Enable AXI: unchecked
Use MCB's Extended Performance Range: Unchecked
Memory Type for Bank 3: DDR3 SDRAM
Memory Type for Bank 1: None
Options for C3 - DDR3 SDRAM
: 400
: MTJ41J64M16XX-187E
C3 - DDR3 SDRAM
: RZQ/6
RTT () - ODT: RZQ/4
:
C3 - DDR3 SDRAM
32- 32-
Port0:
1:
2:
3:
4:
Port5: unchecked
: row-bank-column
FPGA C3 - DDR3 SDRAM
=== ===
Matlab 64- , DDR3 , .
wire [00:00] cmd_instruction = usb_data[63:63];
wire [27:00] cmd_address = usb_data[62:37];
wire [31:00] cmd_data = usb_data[31:00];
ug388 :
20: 26 .
C_MEM_ADDR_WIDTH = 13
C_MEM_BANKADDR_WIDTH = 3
C_MEM_NUM_COL_BITS = 10
C_P0_DATA_PORT_SIZE = 32 // 32-bit data ports
C_P0_MASK_SIZE = 4 // 4 bytes = 32 bits (1 mask bit = 1 entire data byte)
26-27: .
pX_cmd_addr [29: 0]: 30- , = "00", (32 ) 4 .
pX_cmd_bl [5: 0]: 1 0.
pX_cmd_instr [2: 0]: : write = "000" read = "001".
28: .
- pX_wr_mask [PX_MASKSIZE-1: 0]: 4- "0000", 4 .
=== ===
, :
assign p0_mcb_cmd_instr = {2'b00, cmd_instruction};
assign p0_mcb_cmd_addr = {2’d0, cmd_address, 2'd0};
assign p0_mcb_cmd_bl = 6'd0;
assign p0_mcb_wr_data = cmd_data;
assign p0_mcb_wr_mask = 4'd0;
localparam C3_MEM_BURST_LEN = 8;
=== ===
- , ?
- , .
,
.