X86_64 single core memory barrier

Question

In x86_64, Intel documentation, section 8.2.3.2, volume 3A, states:

The Intel-64 memory model allows you to reorder neither the load nor the stores using the same operation. That is, it ensures that loads are visible programmatically and that stores are displayed programmatically

I need to be sure that the variable will not be reordered when writing to the memory address.

I want to avoid atomic xchgbecause of the high cost that it includes. And in my application, another processor reading this value knows how to handle an incomplete state.

Some code:

cli();
compiler_unoptimization(); // asm volatile("":::"memory")
volatile uint *p = 0x86648664; // address doesn't matter
*p = 1;
... // some code here
*p = 0;
sti();

So, do I correctly assume that:

• 1) cpu will not do * p = 0 before * p = 1, without the need for a sfence

• 2) (gcc clang) p, asm ( , ?).

Answer 1

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