Create TIE cells with Yosys?

Question

I use Yosys to synthesize my RTL construct, which includes a pair of literal constants, such as bound output ports, as in the following code:

module my_module (
    input a,
    input b,
    output c,
    output d);

    assign c = a & b;
    assign d = 1'b1;
endmodule

In this case, the conclusion dwill obviously always be logical. The thread I use includes a call abc -liberty my_stdcells.libto map combinatorial logic to standard cells provided by the library, followed by calls cleanand write_verilog.

I also use a cell library that contains cells TIELOand TIEHI, but the synthesized Verilog connection list does not contain instances of these cells, and instead displays literal constants, as in the above example.

Maybe I could write a script to post-process the synthesized netlist to replace these literals with cell instances TIE*from the library, but I'm wondering if I can get Yosys to do this for me somehow, resulting in something like

TIEHI tiehi_d_inst(.Y(d));

for the line assign d = 1'b1in the above code.

Answer 1

The team you are looking for hilomap. For example, to display the cells TIEHIand TIELOwith the conclusions Y, use something like:

hilomap -hicell TIEHI Y -locell TIELO Y

TIEHI/TIELO . -singleton, TIEHI/TIELO .