I think you mixed up your terminology.
The delay is introduced into the pipeline by the processor to eliminate the dangers of the data (situations where the data necessary to process the instruction is not yet available. NOP
Is just an instruction without a side effect.
Benches
Recall stage 5 of the classic RISC pipeline conveyor :
- IF - extract instructions (fetch the next instruction from memory)
- ID - Decoding the instruction (find out what the instruction is and what the operands are)
- EX - ( )
- MEM - ( )
- WB - ( )
:
add $t0, $t1, $t1
sub $t2, $t0, $t0
, . : (RAW); .
sub
add
EX, add
MEM - WB:
+------------------------------+----+----+----+-----+----+---+---+---+---+
| | CPU Cycles |
+------------------------------+----+----+----+-----+----+---+---+---+---+
| Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
+------------------------------------------------------------------------+
| 0 | add $t0, $t1, $t1 | IF | ID | EX | MEM | WB | | | | |
| 1 | sub $t2, $t0, $t0 | | IF | ID | EX | | | | | |
+---------+--------------------+----+----+----+-----+----+---+---+---+---+
, , .
+------------------------------+----+----+----+-----+----+----+-----+---+----+
| | CPU Cycles |
+------------------------------+----+----+----+-----+----+----+-----+----+---+
| Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
+----------------------------------------------------------------------------+
| 0 | add $t0, $t1, $t1 | IF | ID | EX | MEM | WB | | | | |
| 1 | sub $t2, $t0, $t0 | | IF | ID | S | S | EX | MEM | WB | |
+----------+-------------------+----+----+----+-----+----+---+---+---+-------+
NOPS
NOP
- , ( ). MIPS nop
MIPS sll $zero $zero 0
.
5 . , .
j label
nop
MIPS, , . (, spim
-delayed_branches
)