Wait for height_edge (clk) vs if rising_edge (clk)

Question

I came across two styles of process instruction in VHDL.

process(clk)
begin
    if rising_edge(clk)
....do something....

Other

process
begin    
    wait until rising_edge(clk)
    ....do something....

What are the advantages and disadvantages of each method.

Answer 1

Assuming that part of the ...second example does not have an operator wait, the two forms are semantically equivalent.

They will behave the same in the simulation.

However, the first form is the recommended style for synthesis and will be considered more readable by many.

Answer 2

Both forms are equivalent for synthesis in Vivado. The second form waitcan be considered more compact, because it "preserves" the level of indentation.

Answer 3

Essentially, the second type is only useful in simulation. The wait statement takes time to flow between the individual statements within the process, which is in contrast to the hardware synthesis process. This usually manifests itself in a simulation stimulus or diagnostic process. In the first form, the process is triggered by a synchronization event and is performed in one step, representing synchronous logic.