What is a good "template" synthesis of a Joss script?

Question

I want to write my own synthesis Yosys script. What is a good template for? The manual and the web page contain various examples, but there is no “authoritative” greeting example.

Answer 1

The command synthruns the recommended script for general purpose synthesis tasks. See help synthfor a complete list of commands invoked by this meta command.

Your script must either borrow from synthor just call synthto get general-purpose material. Many scenarios are called synth -run coarsefor the coarse-grained part of the synthesis, and then continue to tune the sequence of commands for the synthesis of small grains. See for example synth_xilinx.

To synthesize an ASIC in a library in freedom format, use the following script as a starting point:

# read design 
read_verilog mydesign.v

# generic synthesis
synth -top mytop

# mapping to mycells.lib
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib
clean

# write synthesized design
write_verilog synth.v

For scripts that perform a formal review, a less aggressive set of optimizations is often required. In this case, the following sequence of commands is usually a good starting point for the “synthesis” part of the formal verification flow:

hierarchy [-check -top <top-module>]
proc; opt; memory [-nomap]; opt -fast; check -assert

Answer 2

mycells.lib mycells.v , yosys. yosys GitHub "examples/cmos", cmos_cell.lib cmos_cell.v.

read_verilog counter.v
read_verilog -lib cmos_cells.v

proc;; memory;; techmap;;

dfflibmap -liberty cmos_cells.lib
abc -liberty cmos_cells.lib;;

write_verilog synth.v

( , , .lib .v, NAND NOR- AND OR.)