Verilog Signed Overflow Overflow Detection

Question

Beginner is here. I am trying to encode a simple 16-bit microprocessor in Verilog and implement it on Spartan 6. ALU implements all signed operations (without any unsigned operations at all). All inputs are wires and signed. The result is stored in a signed register.

My problem is finding a reasonable way to detect overflow. It doesn’t currently matter how fast the overflow occurs, since everything he does causes an error and stops the system.

I believe that I understood how I can detect overflow in addition and subtraction, but I would like to guarantee anyway.

Here's the complement, where o is the overflow flag register:

if((a_in >= 0) && (b_in >= 0) && (res_out < 0)) o <= 1'b1;
else if((a_in < 0) && (b_in < 0) && (res_out >= 0)) o <= 1'b1;
else o <= 1'b0;

Here's the subtraction:

if((a_in >= 0) && (b_in < 0) && (res_out < 0)) o <= 1'b1;
else if((a_in < 0) && (b_in > 0) && (res_out >= 0)) o <= 1'b1;
else o <= 1'b0;

a_in b_in, , , ( ).

, , , , C ++. .

a_in b_in 16 . res_out , 16 . 33 , , .

. .

Answer 1

Overflow underflow , 4- , 5 .

+ ve

  3 : [0]0011
+ 3 : [0]0011
= 6 : [0]0110

  -3 : [1]1101 
+ -3 : [1]1101
= -6 : [1]1010

: +8, 4 .

  +7 : [0]0111
  +1 : [0]0001 
  +8 : [0]1000

underflow: -9, 4 .

  -8 : [1]1000
+ -1 : [1]1111
  -9 : [1]0111 

, 1

localparam WIDTH = 4;
localparam MSB   = WIDTH-1;
logic [WIDTH-1:0] a;
logic [WIDTH-1:0] b;
logic [WIDTH-1:0] result;
logic extra;
logic overflow;
logic underflow;


always @* begin
  {extra, result} = {a[MSB], a} + {b[MSB], b} ;
  overflow  = ({extra, result[MSB]} == 2’b01 );
  underflow = ({extra, result[MSB]} == 2’b10 );
end

, , 32- . 16.

, , .

NB: , 1 , . / .

, 16 * 16 32- . , 33 . , , . ALU.

, 32- max/min 16- , 16- .

Answer 2

, 7 -3, .

  7 : [0]0111
- 3 : [1]1101
= 4 : [1]0100

, , , +4.