Verilog bit change location

Question

Assuming I have a register reg [15:0] my_regthat contains a 16-bit signed sample:

How to find the place where the first bit change is? So, assuming that my_reg = 16'b0001011011010111, how can I find out that the first change from 0to 1is on my_reg [12]? The same goes for numbers starting with 1negative numbers, for example. my_reg = 16'b1111011011010111would be interested in the position of the first appearing 0(which in this case 11).

The ultimate goal (add a little context) is to implement the digital integrated automatic gain control FPGA (AGC).

Answer 1

The same method as described above, but parameterized. Use XOR shifted by one bit to determine where the bit is changing, then use a downstream priority encoder to output the first change location. I filled up my_reg[0], so the first bit does not create a delta.

localparam width=16;

reg  [width-1:0] my_reg;
wire [width:0] delta;
reg  [$clog2(width)-1:0] index; // Note: $clog2 was added in IEEE1364-2005
integer i;

assign delta = my_reg ^ { my_reg, my_reg[0] };

always @* begin
  index = 0;
  for (i=0; i<width; i=i+1)
    if (delta[i])
      index = i;
end

Above the code on the EDA playground (thanks for heads-up on this, BTW) http://www.edaplayground.com/x/3uP

Answer 2

A two-way solution for this is as follows:

my_reg1_diff = (my_reg1 ^ (my_reg1 << 1))>>1 ;
my_reg1_diff_pos = $floor($ln(my_reg1_diff)/$ln(2));    //log2 of (my_reg1_diff)

See a working example of edaplayground.com .

, starbox. log2, case. . edaplayground.com .

Answer 3

- .

, XOR 16- my_reg, case, , .

:

, . , , , .

wire [3:0] my_reg;
wire [2:0] xor_bits;
reg [2:0] count;

// XOR bits
assign xor_bits = {my_reg[3] ^ my_reg[2], my_reg[2] ^ my_reg[1], my_reg[1] ^ my_reg[0];

always @ (*) begin
case (xor_bits)
000: change_location= 4;
00X: change_location= 3;
0XX: change_location= 2;
default: change_location= 1;
endcase

end