Verilog signed vs unsigned samples and first

Question

Assuming I have a register reg [15:0] my_regthat contains a 16-bit signed sample:

How to convert a sample from signed to unsigned? I read this Wikipedia article and am aware of a 2-bit add-on for signed numbers, but how can I do this conversion to Verilog efficiently? (I don’t know if it is my_regpositive or negative, and it changes in every measure = I get a new pattern on every positive edge of the clock).

The ultimate goal (add a little context) is to implement the digital integrated automatic gain control FPGA (AGC).

EDIT: as I said, I divided the two questions into two different posts. See Another here

Answer 1

In Verilog, a reg contains unsigned binary data - it's just a matter of interpretation. The bit values ​​remain unchanged, subtraction and addition are always performed using two additions.

For example, we can look at a 4-bit value and see how numbers can be interpreted:

  Binary Unsigned  signed  
  1000          8      -8
  1110         14      -2
  1111         15      -1    
  0001          1       1
  0010          2       2
  0111          7       7

I think you want to calibrate these numbers to a positive scale, -8 becomes 0, 0 becomes 8, 7 equals 15. This would be done by adding 1 to the MSB position . In our 4-bit example:

  Binary   Signed  Addition Unsigned result
  1000         -8  +1000    0000   0
  1110         -2  +1000    0110   6
  1111         -1  +1000    0111   7
  0001          1  +1000    1001   9
  0010          2  +1000    1010   10  
  0111          7  +1000    1111   15

:
1. Verilog: .
2. Verilog .

, :

reg signed [15:0] my_reg;

:

reg signed [15:0] my_reg;
reg        [15:0] my_reg_unsigned;

always @* begin
  if (my_reg < 16'd0) begin
    my_reg_unsigned = -my_reg ;
  end
  else begin
    my_reg_unsigned = my_reg ;
  end
end

, , - , unsigned, :

always @* begin
  my_reg_unsigned = my_reg ;
end

, my_reg_unsigned $signed(my_reg_unsigned)