, , , .
1MHz clock 1000000 . , 1 1/1000000 1us. 1 , 1000000 1us, , 1000000.
, 1 sec delay @ 1MHz:
Delay_1sec: ; For CLK(CPU) = 1 MHz
LDI dly1, 8 ; One clock cycle;
Delay1:
LDI dly2, 125 ; One clock cycle
Delay2:
LDI dly3, 250 ; One clock cycle
Delay3:
DEC dly3 ; One clock cycle
NOP ; One clock cycle
BRNE Delay3 ; Two clock cycles when jumping to Delay3, 1 clock when continuing to DEC
DEC dly2 ; One clock cycle
BRNE Delay2 ; Two clock cycles when jumping to Delay2, 1 clock when continuing to DEC
DEC dly1 ; One clock Cycle
BRNE Delay1 ; Two clock cycles when jumping to Delay1, 1 clock when continuing to RET
RET
Delay3, 4 , DEC=1, NOP=1 BRNE=2 Delay3. , 4 250 ( dly3) - 1000 1000us= 1ms.
Delay2 Delay3 125 ( dly2). , 125ms.
, , Delay1 Delay2 8 ( dly1). , 1000ms 1 second.
. , 1sec, Delay2 Delay1. , 1sec , dly1, dly2 dly3 , , t21 .
2. , . , timers .