From the handbook Cortex-R , may not Cortex-R specific
Asynchronous interrupt mask
The nature of asynchronous interrupts means that they can occur when the processor processes another interrupt. If an asynchronous interrupt throws a new exception in this situation, the values r14_abtandSPSR_abtoverwritten. If this happens before data is pushed onto the stack in memory, information about the state of the first interrupt will be lost. To prevent this from happening, the CPSR contains a mask bit, bit A, to indicate that an asynchronous interrupt cannot be accepted. When an A-bit is set, any asynchronous interrupt that occurs is held on hold by the processor until the A-bit is cleared when the exception is actually thrown. A-bit is automatically set upon interruption, IRQ interruptions, or FIQ exceptions and to reset. You should only clear the A-bit in the interrupt handler after the status information has either been stored in memory or is no longer required.
My question is: if I have a bit Adisguised with reset, how can I find out if an asynchronous interrupt is waiting? Is it possible to clear pending external interrupts without smearing a bit Aand eliminating an exception? Or, in general, is there advice on clearing the bits Aafter reset?
Apparently, something in my current load chain has a pending external interrupt (but only after hard power). I would like to include external interrupts, but for a special case, the first external interrupt in the exception code seems rather cumbersome.
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