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What is the standard HW test technique when there are cases where RTL and Goldenmodel can produce different but correct results?

I have a UVM test bench (limited random check) for my equipment model. My golden model is written in systemC and C ++. I have cases where the result of my equipment will not match the result of the software, but both of them can be potentially correct.

As an example, my HW does some memory management (allocation, freeing resources), and this leads to some other logic in the pipeline. Depending on the "when", the HW receives a alloc or dealloc request and some temporary arbitration policy, it produces some results. There is no concept of time in the gold model, and in some cases the output will not correspond to HW, but both the HW and the gold model can be potentially correct.

What is the standard way to test this kind of scenario? When both the gold model and the HW outputs are correct, but they differ in value, I’m not quite sure if a landing score can help verify the correctness. I am new to this area. So any tips / pointers would be much appreciated.

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One of the goals of UVM is to increase the level of test abstraction beyond the level of hardware output. If you have knowledge that the result is correct for a given random stimulus, you need to put this knowledge on the scoreboard. The job of the monitor should make a transaction that deletes most of the information about the temporary domain and sends it to the scoreboard for processing.

Let's take a simple case of a non-standard scoreboard where you send packets to the DUT for routing, but they exit in a different order. Your reference model may produce different orders, but all the packages that came in should eventually come out after a certain period of time. You should check on the scoreboard that the packages were received without checking the order, or he checks a lot of the order imposed by the requirements of the project.

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Source: https://habr.com/ru/post/1541359/

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