Understanding Makefile Syntax and Variables

Question

I am reading a large Makefile, part of which I do not understand:

$(IREJECTION): $(IREJECTION:%$(MACH64).o=%.cpp)
        $(CPP) $(CPPDLIBOPTS) -c $(@:%$(MACH64).o=%.cpp) -o $@

In this script (note that I removed the unnecessary variables to avoid verbosity), which means the following

• $(IREJECTION:%$(MACH64).o=%.cpp) (in the first line)
• $(@:%$(MACH64).o=%.cpp)? (on the second line)

Also, what does this form mean A: B? How in:

 $(IREJECTION): $(IREJECTION:%$(MACH64).o=%.cpp)   #on the first line
 <---- A ---->  <------------ B --------------->   #first instance of A: B
                <--- A ----> <-------- B ------>   #second instance of A: B

As you can see, there are two instances of the form A:B- the second is inside B. I also see a resemblance here:

$(@:%$(MACH64).o=%.cpp)   #on the second line
 <A> <---------B------->

Please help me figure this out.

Answer 1

You have a rather complicated example, I think. There are many things in it.

Rule / Recipe

A: B
    <command>

• A - target
• B - dependence
• <command>- the command to be executed for the assembly A("Recipe")

target: dependency "". , "" "".

( A, B, <command>)

make B A. B , <command>

$(IREJECTION) make ( - , IREJECTION:=somefile.o)

make $(IREJECTION) .

:

$(var:a=b) <.. > var, "a" "b" .

:

 foo := a.o b.o c.o
 bar := $(foo:%.o=%.c)

bar a.c b.c c.c.

$(IREJECTION:%$(MACH64).o=%.cpp) IREJECTION, $(MACH64).o ( MACH64) .cpp.

$@ . "".

http://www.gnu.org/software/make/manual/make.html

Answer 2

A: B , A, B. , B , , A. A, make A.

Answer 3

:

, irejection.mach64.o irejection.cpp

, smth

irejection.mach64.o : irejection.cpp # means target : dependencies
    $(CC) irejection.cpp -o $@ # $@ is a special variable - the target (output)

$(MACH64) is .mach64 $(IREJECTION) is irejection$(MACH64).o, irejection.mach64.o

$(IREJECTION:%$(MACH64).o=%.cpp) irejection.cpp

$(@:%$(MACH64).o=%.cpp) , $@ $(IREJECTION)

, .

It seems to me incomprehensibly confused. A cleaner way would be like:

%$(MACH64).o : %.cpp
    $(CC) -c $@ $<

%are "wildcards", $<is the first dependency, $@is the output

see http://www.gnu.org/software/make/manual/make.html#Automatic-Variables

http://www.gnu.org/software/make/manual/make.html#Pattern-Rules