X86 PIC, is it correct for QEMU to raise interrupts on all processors?

Question

I recently had to get around the patented OS problem with x86 PIC, where the expected OS interrupt timer is ONLY on CPU0. I turned on IO-APIC to get around this and do processor steering so that interrupts go only to CPU0. The problem is resolved.

I was told that our equipment was broken to do this. that is, interrupt the interrupt timer on all CPUs when only the PIC is used. "Hardware" - QEMU / KVM.

Is there a QEMU / KVM error? Is the OS invalid?

My suspicion is that QEMU / KVM does this correctly, and the OS should be able to handle timer interrupts on the CPU! = 0 ...

Answer 1

I think it's true, PIC usually only interrupts CPU 0, including timer interrupts. Most operating systems will not try SMP with PIC, since CPU1 is all that cannot receive or receive any interrupts (including some kind of timer interrupt to schedule the process); for example, Linux with "noapic" disables everything except CPU0. I think this OS hit an odd angle in qemu.