Why is GNU always reconfiguring my project?

Question

I have the following Makefile in a directory full of files .cppand .h:

CFLAGS=-g -std=c++0x -Wall -pedantic -Wextra -D __STDC_LIMIT_MACROS -D __STDC_FORMAT_MACROS -O0
CXX=g++
LDFLAGS=-lgmp -lmathsat -lz3

all: Foo.o Bar.o
        $(CXX) $(CFLAGS) -o myexe Foo.o Bar.o $(LDFLAGS)

depend: .depend

.depend: $(wildcard *.cpp)
        rm -f ./.depend
        $(CXX) $(CFLAGS) -MM $^ > ./.depend

include .depend

%.o: %.cpp
        $(CXX) $(CFLAGS) $(INCLUDE) $< -c

clean:
        rm -f *.o myexe

When I click make, it invariably performs the last step (linking), even if none of the files .ohave changed. How can I prevent makethis from happening? I would expect makefor output Everything up-to-dateor something like that.

I am on an i686 GNU / Linux machine with GNU Make 3.82 and g ++ version 4.8.2.

Answer 1

, all. all all. myexe. , make, , all, , , myexe , make.

, make :

all: myexe
    echo Build done

myexe: <myexe dependencies go here>
    $(CXX) $(CFLAGS) -o myexe $(wildcard *.o) $(LDFLAGS)

Answer 2

. all. all all, .

, all myexe, all, : all: myexe.

( GNU Make , .PHONY, .PHONY: all depend clean.)

Answer 3

make - .

( ), .
, , .

, , : target all all, make .

, all - , . .PHONY .