Level trigger control and nested interrupts

Question

[Updated question since GIC v2 has 3 registers ACK, EOIR, DIR]

This is the most basic question I need for someone else to clarify and say that the sequence below is correct.

In the next arc

  [Core] ----- [ Interrupt Controller ] --Level Triggered -- [Device]

•  
• a. The device raises the level and informs the interrupt controller  
• b. The interrupt controller starts the interrupt core. (Assuming core interrupts are enabled)  
• c. Assuming GIC interrupt controller (used with ARM) and has 3 registers 
  •     
  • - Deactivate interrupt (GICC_DIR)    
  • - ACK interrupt (which returns the IRQ number), (GICC_IAR)    
  • - end of interrupt register (GICC_EOIR) 
   

. GICv2 GICC_CTLR.EOImode 1 .
: 3 (ARM IHI 0048B.b ID072613)

, ,

•   
• . , Core ACK IRQ, , .  
• . Core . Core ACK IRQ, .

.

• A. Core GIC, , . Core
• . Core GICC_EOImode = 1 EOIR. Core

(A) (B)

Q1. ?

?

Answer 1

Q1. ?

, . , . . , . , , , , GIC , .

Q2. (e) ​​ (g), ​​

. , . , FIFO . FIFO , .

, . .... . (GIC) , . .

.

, . , FIFO , . , .

IRQ . f IRQ , . irqActive 0x300-0x304 , , IRQ. ISR . , , ISR .

• GIC.
• GIC ​​ARM .
• GIC ACK ISR.
• IRQ .
• , irqActive . ( ISR ).
• , .

( ) , "-". , . . , .

3.2.1 ,

• IAR - .
• EOIR - ; .
• DIR - , ( ).

, . , EOIR ISR; .

Edit:

.

. Core GIC, , . Core

, .

. Core GICC_EOImode = 1 EOIR. Core

EOIR + , ( , , "B" ).

, Linux, , . ISR ( ), ; "IRQ-k" . , Linux afaik.

Edit2: GICC_CTRL.EOImode =1 . , . , . EOIR , . DIR , . GICC_CTRL.EOImode=0, , . , (, , ); IRQ, .