Below is the stream mentioned in the Cortex A Prog Guide. I have a few questions on the text.
Then, the interrupt handler must take the following steps after an IRQ exception occurs, and control is passed to the interrupt handler, as described earlier.
• The interrupt handler saves the context of the interrupted program (ie, imposes on the alternative mode in kernel mode any registers that will be damaged by the handler, including the return address and SPSR_IRQ).
Q> What is the alternative kernel mode stack here ?
• It determines which interrupt source should be processed and cleans the source in external equipment (preventing it from immediately triggering another interrupt).
• The interrupt handler switches the processor to another kernel mode, leaving the CPSR bit I (interrupts are still disabled).
Q> From IRQ to SVC mode with CPSR.I =1 . Right ?
• The interrupt handler stores the return address of the exception on the stack (the stack for the new mode in the kernel memory) and re-enables interrupts.
Q> Are there 2 stacks here ?
• It calls the appropriate C handler for the initial interrupt (interrupts are still disabled).
• Upon completion, the interrupt handler disables the IRQ and issues the return address of the exception from the stack.
• It restores the context of the interrupted program directly from the alternative kernel mode stack. This includes PC recovery and CPSR, which switches to the previous run mode.
Q> How is the nesting done here ? I am bit confused here...