VHDL / PlanAhead error: <countr> remains a black box because it does not have a binding object

Question

How can I fix this error? PlanAhead 14.7 is able to synthesize, but not correctly mimic this simple counter. The "dut: portr port map" instance remains with a red question mark in the sources tab. I made sure that all signals are created correctly, tried to re-add sources, tried to create a new project. Working with IP cores can cause this problem, but I don’t think so.

Design Source:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity countr is
Port (clk : in std_logic;
      reset : in std_logic;
      output: out std_logic_vector(4 downto 0)
 );
end countr;

architecture Behavioral of countr is
signal count : std_logic_vector(4 downto 0);
BEGIN

proc_1: process(clk, reset)
begin
    if reset = '1' then
        count <= (others => '0');
    elsif rising_edge(clk) then
        count <= std_logic_vector(unsigned(count) + 1);
    end if;
end process;
output <= count;
END Behavioral;

Simulation Source:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cntr_TB is end cntr_TB;
architecture Behavioral of cntr_TB is
component countr is
port(clk  : in std_logic;
    reset : in std_logic;
    output: out std_logic_vector(4 downto 0)
 );
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal output : std_logic_vector(4 downto 0) := "00000";
signal endOfSim : boolean := false;      
constant period : time := 20 ns;
BEGIN
dut: countr port map (clk => clk, reset => reset, output => output);
clkStimulus: process(clk)
begin
    if endOfSim = false then
        clk <= not clk after period/2;
    end if;
end process;
stim: process
begin
wait for 40 ns;
reset <= '0';
wait;
end process;
END Behavioral;

Answer 1

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