Is there a way to do nested generation statements in Verilog?

I am trying to reduce some code using generate expressions, but I can only figure out how to do this through nesting, but I do not believe that this is allowed.

I have, essentially, some running for the loop (which require generation), and inside them I want to run one of the three sections of the code depending on the value that is set when creating the code (which then requires the second to be generated). Is there any way to do this and make the tools happy?

Here is a quick overview of what I'm trying to do:

    //TAPS_PER_CHAN is a value defined when the code is built
genvar srcNode, dstNode, tapIdx;
 generate
  for (dstNode=0; dstNode<NODES; dstNode=dstNode+1)
    begin: dstForLoop
    generate
        if(TAPS_PER_CHAN <= 4)
        begin
            call module one
        end    
        else if (TAPS_PER_CHAN <= 8)
        begin
            call module two
        end      
       else if (TAPS_PER_CHAN <= 16)
       begin  
            call module three
        end
    endgenerate
    end
endgenerate
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2 answers

, generate/endgenerate.
. IEEE Std 1800-2012 & sect; 27 .

    //TAPS_PER_CHAN is a value defined when the code is built
genvar srcNode, dstNode, tapIdx;
 generate
  for (dstNode=0; dstNode<NODES; dstNode=dstNode+1)
    begin: dstForLoop
    // generate <-- remove this
        if(TAPS_PER_CHAN <= 4)
        begin
            call module one
        end    
        else if (TAPS_PER_CHAN <= 8)
        begin
            call module two
        end      
       else if (TAPS_PER_CHAN <= 16)
       begin  
            call module three
        end
    // endgenerate <-- remove this
    end
endgenerate

example

+3

Generate, / Verilog (if-else, for-loop) vs Parameter + gen_var (if-else, for-loop) , TAP_PER_CHAN , , verilog/simulator :

NC-Verilog, Ascent-Lint Novas-nTrace.

TAP_PER_CHAN; genvar srcNode, dstNode, tapIdx;   for (dstNode = 0; dstNode       else if (TAPS_PER_CHAN <= 8)                         
     else if (TAPS_PER_CHAN <= 16)      
                    //endgenerate < -    endgenerate

0

Source: https://habr.com/ru/post/1533369/


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