Need help Disable re-alignment of comments after signals in the port list. (Verilog mode)

Question

Here is my problem, I define a list of ports as such:

module spi_jstk ( 
                  input        clk,     // System Clock (40MHz)
                  input        reset,   // Async Reset
                  input        START,   // Initialize SPI Transfer
                  input [39:0] DATA,    // Input Data to Transfer
                  input        SS,      // Chip Select
                  output       SCLK,    // Serial Clock
                  input        MISO,    // Master In Slave Out
                  output       MOSI );  // Master Out Slave In

Looks good.

Now let's say I add a new signal to this list or just press TAB and this happens:

module spi_jstk ( 
                  input        clk, // System Clock (40MHz)
                  input        reset, // Async Reset
                  input        START, // Initialize SPI Transfer
                  input [39:0] DATA, // Input Data to Transfer
                  input        SS, // Chip Select
                  output       SCLK, // Serial Clock
                  output       NEW, // NEW SIGNAL
                  input        MISO, // Master In Slave Out
                  output       MOSI );  // Master Out Slave In

Not sure why he did this with my comments, does anyone know how I will disable this? This is really frustrating.

Another thing that I do not understand is that if I click TAB on the list of regular signals (not in the list of ports), this does not get confused with my comments. These comments remain aligned after the tab.

   // Signals
   reg [2:0]  q_state, n_state;
   reg        q_clk;
   reg        q_sck;    //1 MHz ticks
   reg [7:0]  q_mosi;   //1 MHz ticks  
   reg [7:0]  q_miso;   //1 MHz ticks

Does anyone know how I can fix this? Thank.

Answer 1

auto-lineup. C-h v verilog-auto-lineup enter

Type of statements to lineup across multiple lines.
If 'all' is selected, then all line ups described below are done.

If 'declarations', then just declarations are lined up with any
preceding declarations, taking into account widths and the like,
so or example the code:
    reg [31:0] a;
    reg b;
would become
    reg [31:0] a;
    reg        b;

If 'assignment', then assignments are lined up with any preceding
assignments, so for example the code
    a_long_variable <= b + c;
    d = e + f;
would become
    a_long_variable <= b + c;
    d                = e + f;

, , , ( M-x Verilog-Submit-- RET). , verilog-auto-lineup.

1) emacs . M-x customize-variable RET verilog-auto-lineup RET. .

2) :

(setq verilog-auto-lineup nil)  ;; disable completely

(setq verilog-auto-lineup 'assignment)  ;; disable only for declarations