Intermediate View for FPGA Compilers

Question

When writing compilers for standard computers, you can target an existing intermediate view (such as LLVM IR) and not worry about the complex architectural differences between the systems. Is there something similar for FPGA?

Answer 1

Not really. Synthesis tools are already very familiar with architecture, so the output list of connections is already configured on the target device.

Closest to all, you could use ASIC tools to target a simple gate library and trigger. This will result in a list of connections with the "lowest common denominator" (although it would then be impractical to redirect to the FPGA as a return from this view, "it was an adder, so I can use the transfer chain" non-trivial.

Update . I see that you want to develop an experimental HDL ...

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