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Using FOR loop in VHDL with variable

Is it possible to create a for loop in the form:

for i in 0 to some_var loop // blah,blah end loop;

If not, is there an alternative way to create the same loop? Since While while allows you to use the variable as a limit, but they are not synthesized in my project.

Thanks Advance,

Boyan Matowski

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2 answers

The variable is great for testbench applications.

For synthesis, you can get the same effect using the static range and the exit condition. Set the maximum range you need.

 for i in 0 to MAX_VALUE loop exit when i = some_var ; // blah,blah end loop;

If your synthesis tool is choking, write a bug report. Both 1076.6-1999 and 1076.6-2004 (VHDL RTL Synthesis Standards) indicate that output conditions are supported for "for" loops with a static range. You may find that support issues regarding the use of a loop label (1076.6-1999) indicate that it is not supported.

If you find an error (or lack of support) and do not report it, your supplier will think that this is a function that you are not interested in, and therefore will not invest in changing your tool.

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Only loop parameters with a static range are synthesized.

You can implement FSM (finite state machine) if some_var has a discrete range. Then write a specific loop for each state.

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Source: https://habr.com/ru/post/1499423/

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