How to access the internal register inside a module in SystemVerilog?

Question

My Verilogs has an architecture / topology:

http://i.imgur.com/irIsD40.png

How can I access the internal registry of IntReg, which is not I / O in IntModule, to do something like this in SystemVerilog?

always @(posedge clk) begin $display ("[Time %0t ps] IntReg value = %x", $time, DUT.IntModule.IntReg); end 

Can bind be used? How?

Answer 1

You do not need to use bind :

 module DUT; bit clk; initial begin repeat (5) begin #5 clk = 0; #5 clk = 1; end end always @(posedge clk) begin $display ("[Time %0t ps] IntReg value = %x", $time, DUT.IntModule.IntReg); end IntModule IntModule (); endmodule module IntModule; reg IntReg = 1; endmodule /* [Time 10 ps] IntReg value = 1 [Time 20 ps] IntReg value = 1 [Time 30 ps] IntReg value = 1 [Time 40 ps] IntReg value = 1 [Time 50 ps] IntReg value = 1 */ 

Answer 2

Yes, you can use interface with bind :

 // Interface interface my_if( input IntReg ); endinterface: my_if // Interface bind bind intModule my_if my_if0( .IntReg(IntReg) ); 

Then enter the register as follows:

 virtual my_if _if = top.DUT.IntModule.my_if0; $display ("[Time %0t ps] IntReg value = %x", $time, _if.IntReg); 

Full example with sim results on EDA Playground: http://www.edaplayground.com/s/4/115