to the right, the m68000 indexed modes use a short extension. In the section “Address register with indirect index (8-bit offset mode)” (d8, An, Xn) BEW is filled in D / A (if Xn is a data or address register), Xn (register number), W / L (for threat Xn content as 16 or 32 bits), scale to 0 (see Note) and 8-bit offset.
on the other hand, in other modes, such as a 16-bit offset, “Address with an offset” (d16, An), the extension is just a word with an offset.
note: short extension word - m68k does not support 2 bits for scale, so it is set to 0; scale on BEW using scale bits, and full extensions are only supported by m68020,40, → cpus. http://etd.dtu.dk/thesis/264182/bac10_19.pdf
source share