VHDL Edge Detection

Question

I want to detect edges on a serial data signal (din). I wrote the following code in VHDL, which works successfully, but edges are detected with a single time period delay. The change output is generated with one delay of the clk_50mhz period on each edge. Can someone help me immediately spot the edges. Thanks.

process (clk_50mhz) begin if clk_50mhz'event and clk_50mhz = '1' then if (rst = '0') then shift_reg <= (others => '0'); else shift_reg(1) <= shift_reg(0); shift_reg(0) <= din; end if; end if; end process; process (clk_50mhz) begin if clk_50mhz'event and clk_50mhz = '1' then if rst = '0' then change <= '0' ; elsif(clk_enable_2mhz = '1') then change <= shift_reg(0) xor shift_reg(1); end if ; end if ; end process ; 

When I changed my code to the next, I was able to detect edges

  process (clk_50mhz) begin if clk_50mhz'event and clk_50mhz = '1' then if (RST = '0') then shift_reg <= (others=>'0'); else shift_reg(1) <= shift_reg(0); shift_reg(0) <= din; end if; end if; end process; change <= shift_reg(1) xor din; 

Answer 1

I found exactly what you need.

Perhaps you should look a little more: http://fpgacenter.com/examples/basic/edge_detector.php .

Edit:

Here you go

 library ieee; use ieee.std_logic_1164.all; entity double_edge_detector is port ( clk_50mhz : in std_logic; rst : in std_logic; din : in std_logic; change : out std_logic ); end double_edge_detector; architecture bhv of double_edge_detector is signal din_delayed1 :std_logic; begin process(clk_50mhz) begin if rising_edge(clk_50mhz) then if rst = '1' then din_delayed1 <= '0'; else din_delayed1 <= din; end if; end if; end process; change <= (din_delayed1 xor din); --rising or falling edge (0 -> 1 xor 1 -> 0) end bhv; 

Answer 2

You must use a combinatorial process to detect the difference without additional loop delays. (You will also need one register to delay input.)

 DELAY: process(clk_50mhz) begin if clk_50mhz'event and clk_50mhz = '1' then din_reg <= din; end if; end process; change <= din xor din_reg;