Is there a way to keep a word matching a term in a 32-bit register instruction

Question

Assume the following x86-32 statement:

add ebx,1 

There are (at least) two ways to collect this opcode:

 81 c3 01 00 00 00 

or

 83 c3 01 

The first stores 1 as a 4-byte word; the second stores 1 as a byte

Is there an instruction that stores 1 as 2 bytes? If not, why?

Answer 1

You stumbled upon the quirk of the x86 instruction set. Intel included a group of instructions in base 83 , the first operand of which is of type Ev , and the second operand is a direct byte, which is interpreted as the same size as the operand of Ev . So, for 83 c3 01 01 interpreted as a 32-bit value; for 66 83 c3 01 , 01 is interpreted as a 16-bit value (and the destination is a 16-bit register ax ). The push copy encoded under barrel 6A behaves the same in size as its only operand.

A broader answer to your question: no, there is no encoding where the 16-bit constant is interpreted as 32-bit.

Source: I wrote a disassembler.

Answer 2

66 81 C3 01 00 ("add bx, 01" in 32-bit mode) can be considered an example of this.

There is no example that does not require redefinition, because there is no need for it. The reason the first example requires four bytes is because it can span the entire 4Gb range. The second uses only one byte, because it is limited to +/- 128 (a total of 256 values). Using redefinition, we can limit the first example to 64kb, but in fact it is not one byte in two, it is two more bytes.

Answer 3

The use of small integers in programming is very common - regardless of the size of the destination. An advantage is the reduction of coding instructions. Many teams support this: IMUL, ADD, ADC, SUB, SBB, AND, CMP, etc. In addition, the addressing mode supports character offset with size bytes to reduce code size.

As for the reasons for "no": I would add that the added savings are minimal compared to saving byte encoding. The ENTER instruction uses a 16-bit immediate, but it is not specified and corrected to update the RSP / ESP / SP register.