For the clock, it may be necessary to set and lock the PLL, set the voltage of the OPP, or other preliminary steps before clk_enable. For example: drivers / clk / clk-highbank.c clk_pll_prepare ()
This procedure has wait loops that rotate until the hardware PLL locks. Cannot do this from the atomic context. Another LWN article talks a bit about the separation of prepare () vs enable ().
PLL and watch details relate to the processor / SoC in question. The block diagrams show the synchronization tree of SoC input pins leading to different PLLs, and then different clock pulses output from each PLL (can also have power domains that can be turned on / off), and the clock individually turns on after the "preparation" is completed. A long story, but I hope this can be useful.
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