What does the syntax (') mean in SystemVerilog?

Question

In the OVM example class, I see the following statement in the constructor:

void'(get_config_int("num_packets", this.num_packets)); 

What is the first part of void'( which should be executed in this statement?

Answer 1

In this case, a single quote is used for type casting. void'() to void'(get_config_int("num_packets", this.num_packets)); means to ignore the return value from get_config_int .

A good simulator should give a warning if the function or return value of the expression is not tied to anything. Using void'() explicitly tells the tool that you want to ignore the return value and do not see a warning.

You can also use other roles, such as int'() , MyPredefinedStruct'() , 9'() . note that providing a constant during casting returns a bit vector. 9'(4'b0101) == 9'b000_0101

See IEEE Std 1800-2012 and read section 6.24 for further explanations and examples.