Generate random values ​​in VHDL function

Question

I have a design that I write / read to / from RAM and perform some calculations on read values. In some cases, I read values ​​from RAM locations where I haven't written anything yet. This is intentional, because in cases where this happens, uninitialized values ​​do not affect the calculation: in these cases, uninitialized values ​​are multiplied by 0.

However, when multiplying an unsigned / signed type that contains the 'U' bits, the result "does not care" (that is, all the output bits of the multiplication 'X' ), even if the other operand is 0. Therefore, I cannot check the final calculation output in my test bank, because it becomes "not caring" (it seems that the "do not care" outputs are interpreted as 0).

To avoid this problem, I wrote a function that resolves any bits of 'U' or 'X' in std_logic_vector to '0' . The functions are as follows

 function f(x : std_logic_vector) return std_logic_vector is variable y : std_logic_vector (x'range); begin y := x; -- pragma synthesis off for i in 0 to x'length-1 loop case x(i) is when 'U' | 'X' => y(i) := '0'; when others => y(i) := x(i); end case; end loop; -- i -- pragma synthesis on return y; end; 

Now I would like to expand the function, not only setting the bits 'X' and 'U' to '0' , but randomly setting them to either '0' or '1' . I tried to use the uniform function in f . The problem is that when I define two semesters inside a function, every time the function f is called, it returns the same std_logic_vector (when it is given the same std_logic_vector ). Since I take this from the description of the uniform function, I have to pass two semesters from outside the function f , because they are changed by the uniform function for the next uniform call.

Is there any way how this can be achieved using a function?

Answer 1

There is a very nice random library here as part of the Open Source VHDL Validation Technique. There is a description and a download link.

http://www.synthworks.com/blog/osvvm/

This allows you to randomize much more than a simple uniform distribution of floating point numbers. In addition to isolating you from the data storage problem that you noted.

Regarding your specifics:

Since I take this from the description of a homogeneous function, I have to pass two seeds from outside the function f, because they are changed by a single function for the next uniform call.

Yes you need. Like this:

 PROCESS VARIABLE seed1, seed2: positive; -- Seed and state values for random generator VARIABLE rand: real; -- Random real-number value in range 0 to 1.0 BEGIN UNIFORM(seed1, seed2, rand); 

So, in your case, you will have to pass these "state" variables to (and from) your function too, which in practice means that this should be a procedure.

Or use the OSVVM library linked above, which allows you to have a shared variable of a protected type that you can use from different places. This preserves its own state “inside” the protected type.

Answer 2

Can I achieve this with a function, or do I need to use a procedure?

Functions do not allow parameters to enter, specify or protect types. This limits your choices. OSVVM randompkg uses a protected type to hide the seed and uses an unclean function to access it. It is quite easy to use. Just download the package from http://www.synthworks.com/downloads and look at RandomPkg_user_guide.pdf.

You can probably get what you are trying to do to work, however it will be a problem. You can define a signal or a pair of signals in your package and use an unclean function (YMMV, I used only unclean functions inside protected types). You can initialize the seeds into signal declarations.

Even with OSVVM, you will need to use an impure function and declare a randomization object as a shared variable.

Jim

Answer 3

about printing an instance name from a VHDL component: ... I did most of my work with the free VHDL GHDL simulator. It has a simple but powerful interface c. Random can be done using c: ... http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_func_rand.html