Is there a way to create a high-level language interpreter implemented in hardware?

Question

Some random thoughts caught me, and I just can't figure it out. I think that since morden processors are just interpreters for different types of assembler languages, is there a way to create some high-level language interpreters directly implemented in hardware using some HDL or even directly designed using logical gates? Meanwhile, I think why this has not been done, some reasons that I can think of now:

• Theoretical reasons. Theoretically, this is impossible, although, in my opinion, it is possible, because either we already have it or the machine we are talking about is just a Turing machine variant, so there is no difference in their nature, but I'm not sure 100%.
• The complexity of the design. It is usually too difficult to create such a complex machine.
• Disadvantages of speed. Even if it is correctly designed and implemented, it still cannot win, because their speed will be disadvantageous.

I'm just curious about this issue.

Answer 1

Ever heard of LISP machines or Symbolics .

I know that the answers are short, and these are mostly links, but the answer is in itself.

Answer 2

This has already been done by the Java processor .

Would it be a very complex instruction set computer (VCISC) that would lead to physically large processors. Some parts of the language are not used as often as others, this leads to rarely used sections of the processor, wasted silicon area.

Large dies for the processor increase yield loss, which increases the cost to the end user. Saving this contributes to smaller simple processors.

Low-power processor designs aim to support RISC over CISC architectures. Supercomputers, such as Deep Blue , used many RISC cores. Most mobile devices use RISC ARM cores.

Answer 3

Burroughs famously had an Algol in Equipment (see B5500) .

Less well known is Burroughs beautiful B1700 , which allows each process to determine the microcode for interpreting the HLL that is used in the process code. Thus, each process can have a different set of HLL instructions; hardware switchable microcodes on a context switch.

A lesson from the RISC world is that it is more economical (and you get a wider market) to create the usual set of instructions and compile the code for your language prior to these instructions. DEC VAX tried to get language specific instructions; it turned out to be faster to use more conventional VAX instructions instead of specific ones.

If you insist, it is probably relatively easy to implement the HLL instruction set using FPGA. (I can imagine that this is a graduate student in the design class of EE). It simply will not be competitive in performance with x86 or another modern RISC chip.