Can I create multiple instances of the same component using a loop?

Question

I have a component:

Component CAU is port ( CLK : in std_logic; RESET : in std_logic; START : in std_logic; V_DIRECTION : in vector_3d; P_ORIGIN : in vector_3d; V_NORMAL_IN : in vector_3d; DOT_A : in vector_3d; DOT_B : in vector_3d; DOT_C : in vector_3d; ID_DATA_IN : in scalar; ID_DATA_OUT : out scalar; V_REFLECT : out vector_3d; V_PASS : out vector_3d; P_INTERSECT : out vector_3d; V_NORMAL_OUT : out vector_3d; T_OUT : out scalar; SUCCESS : out std_logic; FINISH : out std_logic ); end Component; 

And I want to create 8 instances. each is called CAU_inst0 , CAU_inst1 , etc. Each instance is connected as follows:

 CAU_inst0 : CAU PORT MAP ( CLK => CLK_CAU, RESET => RESET, START => start_0_sig, V_DIRECTION => v_direction_0_sig, P_ORIGIN => p_origin_0_sig, V_NORMAL_IN => v_normal_in_0_sig, DOT_A => dot_a_0_sig, DOT_B => dot_b_0_sig, DOT_C => dot_c_0_sig, ID_DATA_IN => id_data_in_0_sig, ID_DATA_OUT => id_data_out_0_sig V_REFLECT => v_reflect_0_sig, V_PASS => v_pass_0_sig, P_INTERSECT => p_intersect_0_sig, V_NORMAL_OUT => v_normal_out_0_sig, T_OUT => t_0_sig, SUCCESS => success_0_sig, FINISH => finish_0_sig ); 

where for each instance of i number 0 is replaced by i . I did to create a Matlab script that created 8 different instances with the correct number. But this is an ugly solution, as it requires 170 lines of the same code with a few changes. Is there a way to create components (and, if possible, corresponding signals) in a loop inside the code to reduce cluter and line?

Answer 1

What you want to use is an expression for ... generate.

Here is an example similar to what you want to achieve:

 architecture GEN of REG_BANK is component REG port(D,CLK,RESET : in std_ulogic; Q : out std_ulogic); end component; begin GEN_REG: for I in 0 to 3 generate REGX : REG port map (DIN(I), CLK, RESET, DOUT(I)); end generate GEN_REG; end GEN; 

In your case, you will need to make all the signals that connect to your block vectors and vector vectors.

For example, if a signal is currently defined as:

 signal v_normal_in_0_sig : std_logic_vector(7 downto 0); 

You will need to change it to:

 type vector16 is array (natural range <>) of std_logic_vector(15 downto 0); signal v_normal_in_sig : vector16(7 downto 0); 

In this case, you can use your signal as v_normal_in_sig(i) to connect to the i th created initialization of your object / component.

Please note that if you use VHDL-2008, you can do the following ...

 type vector_array is array (natural range <>) of std_logic_vector; signal v_normal_in_sig : vector_array(7 downto 0)(15 downto 0);