Two add-ons in verilog

Question

I am trying to create a module that returns two additional representations of (3-bit) input (the first bit is a sign). I think the following code is conceptually correct, but I probably missed something in this structure: when I try to compile, I get the following errors:

(vlog-2110) Illegal reference to net "f_o". (vlog-2110) Illegal reference to net "f_o". (vlog-2110) Illegal reference to net "f_o". 

A search for this error showed that this is usually observed while using the variable as input and output, but this is not my case. Could you please indicate where the error is?

 module ca2 (a_i,f_o); input [2:0] a_i; output [2:0] f_o; always @(a_i[2:0] or f_o[2:0]) begin if (a_i[2] == 1) begin f_o[2] = a_i[2]; f_o[1:0] = (~a_i[1:0] + 'b1); end else begin f_o = a_i; end end endmodule 

Answer 1

In Verilog, undeclared identifiers are considered implicit wire declarations in most cases. Since f_o was not declared, the compiler considers it wired, not variable. This makes the compiler complain about all the assignments.

 // What was typed module ca2 (a_i,f_o); input [2:0] a_i; output [2:0] f_o; // What the compiler implicitly declares wire [2:0] a_i; wire [2:0] f_o; 

To fix this, you can declare a variable or declare both a port and a variable.

 module ca2 (a_i,f_o); input [2:0] a_i; output [2:0] f_o; reg [2:0] f_o; module ca2 (a_i,f_o); input [2:0] a_i; output reg [2:0] f_o; 

Answer 2

f_o must be declared as reg. output reg [2:0] f_o .

Also I'm not sure what you are calculating, this is not a standard addition.

 module ca2 ( input [2:0] a_i, output [2:0] twos_comp, output [2:0] also_twos_comp ); assign twos_comp = ~a_i + 1'b1; assign also_twos_comp = -a_i ; endmodule 

You may be dealing with encoded input, but twos_complement is to deny the number that I would expect the sign bit (MSB) to change. Although we speak of it as a sign bit, it also contains information about the value and, therefore, it cannot simply be turned off and left unchanged.