Testing my HDL code (Verilog / VHDL) without FPGA?

Question

I wrote a module in Verilog using vi as my editor, and now I want to test it. What are my options if I don't have a board? How can I provide my module inputs? Where can I see the results? By the way, I have access to VCS.

Thanks.

Answer 1

You may be looking for a simulator.

First, you need to write a testbench that wraps around your Verilog module and controls the input signals. This testbench can also check if your module output matches the expected result. You can find many guides for writing test sites on the Internet.

This test bench and your module are then “executed” in the simulator. I am not familiar with all the options, but I know that the free Xilinx ISE Web Pack includes a simulator. Modelsim is a commercial package. They also offer a free student edition.

Answer 2

For everyone who has the same question, I found a testing tutorial, like Vortexfive, in the link below:

http://www.asic-world.com/verilog/art_testbench_writing.html