I want to create a macro with several parameters just like $ display.
You can not. Verilog and SystemVerilog do not support variable macros .
The following is a workaround if your goal is to use this to format strings or output, and you don't need to type $sformat everywhere. You can define a macro for a single argument and combine this argument with $sformat . The caveat to this is that you must wrap the argument in parentheses when using a macro.
Note that () for $sformatf are not part of the macro:
`define format_macro(A) \ $write("%s", $sformatf A ); \
Then you can do this:
`format_macro(("a = %d", a)) `format_macro(("a = %d, b = %d", a, b))
By the way, there is an excellent screencast here that shows how to set up UVM messaging. In it, the author shows this macro technique, as well as some other useful tips if you use UVM.
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