The feenableexcept function is a linux function that is not part of standard C or POSIX. You cannot transfer the SIGFPE method.
In fact, you need a different code to enable SIGFPE on the iOS simulator and on iOS devices, because the simulator runs x86 and the device launches ARM.
I think (but did not check) that you can enable SIGFPE by getting fenv_t using the fegetenv function, turning some bits on or off in fenv_t , and then passing it to fesetenv . The definition of fenv_t is processor dependent. Take a look at fenv.h
For ARM, fenv_t contains a field named __fpscr . It is a status and a floating point register . The bits that you allowed to switch are listed in fenv.h as __fpscr_trap_invalid , __fpscr_trap_divbyzero , etc. Presumably you want to enable the __fpscr_trap_divbyzero bit.
For x86, fenv_t contains two fields of interest: __control (control word x87) and __mxcsr (SSE register / status register).
The bits that you can switch to __control are determined by the constants FE_INEXACT , FE_UNDERFLOW , etc., defined in fenv.h I think you need to disable the bit to enable SIGFPE for these exceptions. Check processor manual, ยง8.1.5 .
The bits that you can switch to __mxcsr are determined by the constants _MM_MASK_INVALID , __MM_MASK_DENORM , etc. at xmmintrin.h . I think you need to disable the bit to enable SIGFPE . Check processor manual, ยง10.2.3.
fenv_t fe; if (fegetenv(&fe) != 0) {
You may also need to run #pragma STDC FENV_ACCESS ON for all processors.
Again, I did not check any of this. Good luck.