What is the purpose of the std_logic enumerated type in VHDL?

Question

What is the purpose of the std_logic enumerated type?

 'U': uninitialized. This signal hasn't been set yet. 'X': unknown. Impossible to determine this value/result. '0': logic 0 '1': logic 1 'Z': High Impedance 'W': Weak signal, can't tell if it should be 0 or 1. 'L': Weak signal that should probably go to 0 'H': Weak signal that should probably go to 1 '-': Don't care. 

Answer 1

std_logic is basically a single wire or bit. You can use logical operators on them (and, or, xor, etc.). When modeling design, I believe that I saw only "X", "0" or "1". Obviously you want "0" or "1". "X" indicates that the value is unknown (perhaps it is not connected with anything, or there is a signal in the signal). In addition, std_logic_vector can be used for signals that must be wider than 1 bit. I'm not sure if this answers your question ...

Answer 2

• "X" is usually called by two operators controlling the same signal in opposite directions, that is, "0" and "1"
• 'Z' is used to create the declared output / input.
• 'L' and 'H' are used to simulate a drop-down list or pullup, respectively
• '-' is used when comparing when you do not need certain bits in a vector

Answer 3

The std_logic type was introduced by the IEEE-1164 standard as an exact representative of a single wire or bit. The VHDL language itself does not provide a single-bit type reliable enough to represent "real" logic. That is, to represent all possible states of simulated and synthesized logic in a modern programmable logic device.

At the beginning of the VHDL story, various developers essentially created their own versions of std_logic because of the need to present real-world signals. IEEE-1164 introduced this standardized logical type in order to increase the compatibility of code written by different developers for different architectures.

The wikipedia article for the standard contains a brief description:

http://en.wikipedia.org/wiki/IEEE_1164

Answer 4

In addition to the answers that have already been provided, I find it worth mentioning that STD_LOGIC is what is called an allowed type, which means that the signal takes precedence. For example, 1 and 0 have a higher priority for H or L, so if the signal is controlled with L and a 1 at the same time, the output will be high (logical 1), since 1 has a higher priority than L.

It just so happens that in the order in which you indicated the values, the priority order is indicated in your question, one of the caveats is that some values ​​have the same priority, and therefore, if you conduct them with both of these signals, there is no clear “winner”, so the result is the following “unknown” state (“X” or “W”) in the hierarchy, a simple example: if the signal is controlled with “H” and “L”, the result will be “W”.

The permissions table for STD_LOGIC looks something like this:

 -- --------------------------------------------------------- -- | UX 0 1 ZWLH - | | -- --------------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | 

Answer 5

I observed this behavior in the Xilinx ISim simulator:

• 'U' is the default state for all signals that are not explicitly set with the default value. I recommend setting a default value for each signal.
• 'X' - assigned when the signal is controlled by two or more drivers with different values
• 'Z' is clearly the high state of Z. Keep in mind that this can only be done on hardware with elements that support three states. I recommend using this only for IO contacts, as these resources are rare in the structure.
• '0' and '1' are normal states.
• I have never seen any of the other states, and I do not expect them to apply to FPGAs.

It is not possible to view variables in ISim, but I assume the same rules apply.

Answer 6

std_logic has a permission function

Not only does std_logic have more useful states except 1 and 0 , it also has a specific permission function.

The permission function is the concept of VHDL. This is a type-related function and determines what happens when multiple values ​​of that type are applied to a single signal. Syntax:

 SUBTYPE std_logic IS resolved std_ulogic; 

where std_ulogic is the unresolved (and therefore much less useful) version of std_logic .

In particular, this means that nice things like 0 and 1 lead to X :

 library ieee; use ieee.std_logic_1164.all; entity std_logic_tb is end std_logic_tb; architecture behav of std_logic_tb is signal s0 : std_logic; begin s0 <= '0'; s0 <= '1'; process begin wait for 1 ns; assert s0 = 'X'; wait; end process; end behav; 

This makes an intuitive sense, since we understand X as a state where several incompatible values ​​are applied to the same wire.

std_logic also knows how to resolve any other possible pair of input signals according to the table present on the LRM.

bit , on the other hand, does not have a resolution function, and if we used it in the above example, this would lead to a modeling error in GHDL 0.34.

The possible std_logic values ​​are a good choice as they are standardized by IEEE 1164 and deal with many common use cases.