If the expression is VHDL

Question

Can someone explain why the golden rule when writing VHDL is that the if-then-else statement must be in the process. This is because, within a process, statements are executed sequentially while they are not.

Answer 1

The simple answer is "because the syntax of the language"!

If you want to select a code from some parameters that is not in the process, you can do:

sig <= a when sel = 1 else b when sel = 2 else default_value; 

or

 with sel select sig <= a when 1, b when 2, default_value when others; 

See here for many examples of multiplexer.

Answer 2

Maybe I'm wrong, but I think that the main reason that if statements should be in the process is because the if statement can assign more than one signal, if you want to do the same outside the process, you will need to use more one conditional signal assignment.

For instance:

 process(C0, C1, A, B, C) is begin if C0 = '1' then F <= A; G <= C; elsif C1 = '1' then F <= B; G <= B; else F <= C; G <= A; end if; end process; 

Equivalent conditional assignments of signals outside the process:

 F <= A when C0 = '1' else B when C1 = '1' else C; G <= C when C0 = '1' else B when C1 = '1' else A; 

Answer 3

if else statement: -

 Syntax: if then statements ... [ elsif then statements ... else statements ... ] endif; 

for more information please this